Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
Transistors and other circuits fabricated in semiconductor substrates are continually being reduced in size as semiconductor fabrication technology advances. Such circuits are also increasingly susceptible to damage from ESD events, thus increasing the importance of the ESD protection implemented in integrated circuits.
Typical ESD protection circuits include diodes that are connected between integrated circuit pin connections and power/ground connections. The diodes are designed to turn on if an ESD event occurs, rapidly discharging the ESD event to avoid damage to the functional circuits (e.g. driver/receiver transistors) that are coupled to the connections.
There are many prior-art documents that provide different ways of designing non-planar ESD diodes. For example, US Patent documents U.S. Pat. No. 8,928,083B2. US2016/0020203A1, U.S. Pat. No. 7,560,784B2, US2014/0191319A1, US2006/0063334A1, U.S. Pat. No. 7,964,893B2, US2014/0183641A1, U.S. Pat. No. 9,006,054B2, US2014/0252476A1, U.S. Pat. No. 8,941,161B2, U.S. Pat. No. 9,177,951B2, U.S. Pat. No. 8,927,397B2, US2014/0217502A1, U.S. Pat. No. 9,368,629B2, US2014/0131765A1, U.S. Pat. No. 9,391,060B2, US2015/0014809A1, U.S. Pat. No. 9,318,622B1, US2013/0292745A1, US2015/0091090A1, and U.S. Pat. No. 7,888,775B2 provide various designs of diode FinFET (non-planar ESD diodes), however, due to the in efficacy of heat dissipation mechanisms and much higher packing density of active area (Fins/Nanowires), these designs exhibit an increased self-heating over the device active area, which leads to an early failure.
There are many prior-art documents that provide ways of implementing BJT and SCR-like devices in FinFET technologies such as but not limited to BJT/ggNMOS FinFET, SCR devices in FinFET and bulk FinFET technology, SCR devices with N and P trigger taps for injecting a trigger current (for tuning trigger/holding voltage) in planar SOI technology, and SCR devices with N and P taps (terminals labeled with N-body and P-body) in a different scheme in order to control holding/trigger voltage in planar SOI technology. For example, US Patent documents US2010/0187656A1, US2015/0145592A1, US2007/0262386A1, US2007/0040221A1, US2015/0311342A1, US2012/0049282A1, US2013/0168732A1, US2013/0175578A1, US2013/0168771A1, U.S. Pat. No. 7,166,876B2, U.S. Pat. No. 9,214,540B2, US2016/0064371A1, US2015/0137255A1, US2004/0207021A1, U.S. Pat. No. 6,909,149B2, US2005/0212051A1, US2009/0206367A1, U.S. Pat. No. 7,638,370B2, and US2010/0207161A1, U.S. Pat. No. 9,240,471B2, U.S. Pat. No. 9,236,374B2, U.S. Pat. No. 7,135,745B1, U.S. Pat. No. 8,963,201B2, and US2014/0097465A1 provide ways of implementing BJT and SCR-like devices in FinFET technologies. However, solutions provided in these prior-arts too suffer from high packing density and enhanced self-heating.
Although the advent of non-planar technologies has paved new and efficient ways to replace their planar counterparts by offering beneficial technological solutions to scale conventional transistors, this has come with a price of lowered ESD robustness and high power density in these advanced technology nodes. ESD is a random event that leads to massive flow of current (in amperes) between bodies having different electrostatic potential for sub-500 ns duration. Power density (or volume power density or volume specific power) is the amount of power (time rate of energy transfer) per unit volume. In energy transformers including batteries, fuel cells, motors, etc., and also power supply units or similar, power density refers to a volume. Power density and therefore self-heating across non-planar devices like FinFETs and Nanowire FETs during Electrostatic Discharge (ESD) events is significantly higher compared to their planar counter parts. Such power density and therefore self-heating during ESD events has attributed to various limitations and drawbacks such as, but not limited to higher packing density of non-planar devices, increased active device width/current per unit area, and reduced substrate area available for heat conduction, which leads to early failure and seriously lowered performance of ESD protection devices in non-planar technologies.
Further, it is also observed that most of the existing and currently available prior-arts are centered on carrier transport under ESD conditions, triggering voltage, holding voltage, etc; however none of such known arts have proposed a solution to improve failure current by employing any heat transport mechanism.
There is therefore a need in the art for a solution to reduce self-heating across ESD protection devices in non-planar technologies by employing efficient heat dissipation mechanisms which further leads to improvement in failure current, thereby enhancing product reliability and life expectancy. There is also a need to provide a solution to reduce self-heating across ESD protection devices in non-planar technologies, thereby eventually saving ESD protection area for a given robustness level resulting in lowered chip cost.
All publications herein are incorporated by reference to the same extent as if each individual publication or patent application were specifically and individually indicated to be incorporated by reference. Where a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply.
In some embodiments, numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description used in the appended claims.